The Serial VID interface (SVI)/ Parallel VID interface (PVI) translator,F75125, which can translate PVI to PVI and SVI to PVI for AMD AM2 or AM2+ platform and output a programmable reference voltage of North Bridge voltage (VNB) to an external single phase PWM by decoding serial VID. Or, it can translate SVI to SVI and PVI to SVI for AMD AM2 or AM2+ platform.
In the PVI output application, the F75125 can replace the hybrid (PVI+SVI) or SVI voltage regulator by the original PVI voltage regulator controller to save the extra cost. The F75125 supports VDDIO, VDDA, and CPU power good input, CPU_PG_IN, such as from the south bridge, SB600, to control the signal, VR_EN to enable the VR controller. F75125 supports all AM2+ new features including CORE_TYPE and VFIXEN. The CORE_TYPE is used to indicate AM2 or AM2+ placed, and the VFIXEN paired with SVC and SVD let voltage regulator output a fixed voltage. In this application of the F75125, VID[5] is recommended to pull low ,so the VID output [4:0] is corresponding to output from 0.775 to 1.550V. In concern of mapping SVI to PVI, VID table on-the-fly tuning is constrained in 0.800V to 1.550V. The Voltage Sense Input (VSI)/Voltage Sense Output (VSO) also provide the similar function, but the tuning range up to 2.325V.
In the SVI output application, the F75125 will issue SVI OFF code to VDD_NB to avoid VDD_NB mis-action when AM2 is implemented. In SVI output mode, the F75125 also supports PSI (bit7 of SVI command).
The F75125 is SSOP-28 package and powered by 3.3VSB.
- FEATURES
- PACKAGE
- ATTACHMENTS
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Serial VID Input to Parallel VID Output or Parallel VID Input to Parallel VID Output Translation for Parallel VID Interface Voltage Regulator Controller
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Serial VID Input to Serial VID Output or Parallel VID Input to Serial VID Output Translation for Hybrid/Serial VID Interface Voltage Regulator Controller
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Serial or Parallel VID Mapping Table Is Adjustable to Tune Voltage Regulator Controller Output.
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Programmable Reference Voltage Output for North Bridge Voltage for Over or Under Voltage in PVI Output Mode
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VFIXEN, SVC, SCD Translation to PVI Voltage Regulator Realizes AM2+ Fixed Voltage Output to CPU Function
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Support CORE_TYPE Input to Indicate AMD Processor Family 0Fh,AM2 or 10h,AM2+
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Support VDDIO, VDDA, CPU Power Good, CPU_PG_IN, Input to Generate Voltage Regulator Controller Enable Signal, VR_EN, and CPU Power Good Output, CPU_PG_OUT, to CPU and Voltage Regulator.
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2 Sets of Voltage Sense Input (VSI) and Voltage Sense Output (VSO) for Over Voltage Vcore and VNB beyond Maximum of VID Table, 1.55V.
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I2C Interface Is Built-in to Fine Tune Vcore and VNB output.
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Power Saving Mode Supported in Both AM2+ Platform
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Powered by 3.3VSB and SSOP-28 Package