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The F85004 has four bidirectional translation switches which controlled by the I2C/ SMBus. The upstream pair M_SCL/M_SDA fans out 4 downstream channels. Any individual SCLx/SDAx channel or combination of channels can be selected, determined by the contents of the programmable control register. An active LOW reset (RESET#)input allows the F85004 to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET# pin LOW resets the I2Cbus state machine and causes all the channels to be deselected as does the internal Power-on reset function. Four interrupt inputs (INT3#–INT0#), one for each of the downstream pairs, are provided. One interrupt (INT#) output acts as an AND of the four interrupt inputs. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the F85004. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 6 V tolerant. |
The F85004 is in the 20 pin QFN package (4mm x 4mm) and 20 pin TSSOP package (173mil).