The F75907 is a CMOS integrated circuit that provide bidirectional voltage level translation (up-translation/down-translation) between low voltage (down to 0.8V) and higher voltage (2.2V to 5.5V). Fast-mode Plus (Fm+) I2C-bus or SMBus applications. The F75907 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus enabling two buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds to be connected in an I2C application. This device can also be used to isolate two halves of a bus for voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high impedance when the F75907 is unpowered. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting. The B-side drivers operate from 2.2 V to 5.5 V. This side also supports the standard low-level contention arbitration of the I2C bus and clock stretching. The output low level for this internal buffer is approximately 0.5V, but the input voltage must be lower 0.4V. The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a latching condition from occurring when the input low condition is released. The output pulldown on the A side drives a hard low, and the input level is set at 0.5VCCA to accommodate the need for a lower low level in systems where the low-voltage-side supply voltage is as low as 0.8 V. The B side drivers have the static level offset that prevents I/O drivers from being connected to the static or incremented offset of other bus buffers, while the adjustable voltage bus A side drivers eliminate the static offset voltage. This means that a low signal on the B side translates to nearly 0-V low on the A side, which accommodates smaller voltage swings of lower voltage logic. The A side of two or more F75907s can be connected to allow a star topography, with A side on the common bus. Also, A side can be connected directly to any other buffer with static- or dynamics- offset outputs. Multiple F75907s can be connected in series, A side to B side, with no build-up in offset voltage with only time of flight delays to consider. The F75907 drivers are enabled when VCC(A) is above 0.8V and VCC(B) is above 2.2V. The F75907 has an active-high enable (EN) input with an internal pullup to VCC(B), which allows the user to select when the repeater is active. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. It should never change state during an I2C operation. The EN input should change state only when the global bus and repeater port are in an idle state, to prevent system failures. |
As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered bus. The F75907 has standard open-drain configuration of the I2C bus. The size of these pullup resistors depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to work with Standard mode and Fast mode I2C devices in addition to SMBus devices.
• I2C Bus and SMBus Compatible • Operating supply voltage range of 0.8V to 5.5 V on A side • Operating supply voltage range of 2.2V to 5.5 V on B side • Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V • 2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of the device at 1 MHz and up to 4000 pF at lower speeds • 5.5V tolerant I2C bus and enable input support Mixed-mode signal operation • Active high repeater enable input • Open drain I/O • Latching free operation • Isolate 2 halves of a bus for both voltage and capacitance • Accommodates standard mode and fast mode I2C devices and multiple masters • Support arbitration and clock stretching across repeater • Power-off high-impedance I2C bus pins |
Package: MSOP 8 (3 x 4.9 x 1.1 mm)